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Datatrak signal -- technical details

At the top level, the Datatrak signal consists of sync data and a series of time-multiplexed navigation slots. Each transmitter is assigned one or more slots, which are either master slots (the transmitter generates the slot without a reference) or slave slots (synchronised to a master slot).

The sync data is phase-modulated onto the carrier centre frequency during the sync slot.

Datatrak uses two frequencies, around 10% apart.

  • $F_1$: around 146.455 kHz
  • $F_2$: around 133.2275 kHz

These are the centre frequencies of the two channels used by the UK system.

The Datatrak signal is based on a 1.68-second cycle. In Interlaced systems, two cycles are chained to produce a pair. This provides 24 navigation slots, and is the “dual-cycle interlaced” scheme mentioned in the introduction.

A cycle takes the following form:

$F_1$ Sync and timing 1..8 9..16 Sync and timing 1..8 17..24
$F_2$ Sync and timing 9..16 1..8 Sync and timing 17..24 1..8

Chain 1's master provides the $F_1$ sync and timing, while chain 2's master provides the sync and timing for $F_2$.

:!: TODO

The SYNC data is transmitted by the chain master and used to allow receivers to synchronise themselves to the transmitted signal.

Function Settling period Trigger Gap Clock Gap Data (TX-TX) Data (TX-RX) Settling time Nav. slots
Time 40 ms 40 ms 10 ms 20 ms 10 ms 65 ms 115 ms 40 ms 8 x 80ms

These function as follows (names are from the Mk.II Locator serial interface):

  • Settling periods – each 40ms. These allow time for the receiver to settle when the frequency has been changed.
  • Trigger
    • This is a phase-modulated signal with a modulation depth of $+\pi, -\pi$ ($+180, -180$ degrees).
    • It encodes one bit of the 64-bit synchronisation sequence using either two cycles of a 50Hz sinusoid (a '0') or 1.5 cycles of 37.5Hz (a '1').
    • This is the origin of the “Datatrak Minute” in the clock shown by the Mk.II Locator.
  • Clock
    • This is a phase-modulated signal with a modulation depth of :?:
    • Two bits (one dibit) are encoded in each clock block, giving a total of 128 bits per cycle.

:!: TODO

  • 10ms settling period
  • 20ms “clock” signal
    • This is one cycle of 50Hz sinsuoid, starting at a phase of 0, 90, 180, or 270 degrees. This encodes two bits of the “clock” signal.
    • The exact encoding of the 64*2 = 128 data bits is unknown.
    • The clock provides a coarse time reference which seems to repeat after 65536*64*1.68 seconds, or around 78.843 days (4054784 seconds).
    • The time format used by Mk.II is: AAAAA:BB:CCCC
      • AAAAA is the clock (0 to 65535).
      • BB is the Gold Code (0 to 63) – the bit position in the sync sequence.
      • CCCC is the “Gold Code offset”. This is possibly a value from 0 to 1680 indicating the time within the current cycle slot in milliseconds.
  • 10ms settling period
  • 65ms transmitter-to-transmitter data
    • This is possibly used to send almanac data, or to send commands between transmitters.
  • 115ms transmitter-to-AVL-receiver data
    • This is used to send commands to the receivers.

:!: TODO

During the navigation “slots” two signals are transmitted: first one 40Hz higher than the centre frequency, then one 40Hz below it. These frequencies are known as the “+” (higher frequency) and “-” (lower frequency) signals.

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  • Last modified: 2020/05/31 13:04
  • by philpem