NABU Adaptor model NA-2 internals

:!: This page is a work in progress

Most of the work I've done is on Github: https://github.com/philpem/NABU-Adaptor

I've reverse-engineered the main PCB for the NABU Adaptor. This is in the Github repository, or can be viewed online with Kicanvas.

Input conditioning

The signal from the demodulator enters via a pair of inverters in the clock and data paths (U24B,U24C for data and U24D,U24E for clock). These clean up the edges on the input signals.


The cleaned-up signals are passed into a self-synchronising descrambler formed of three 74LS164 shift registers (U20, U12, U13) and three gates of a 74LS86 quad XOR IC (U21a, U21b, U21d). This circuit is similar to the IESS-308E11 scrambler, with the counter block omitted.

HDLC flag detection and zero-stuffing removal

The input data from the headend is HDLC encoded, subject to the following rules:

  • A byte of value 0x7E is a FLAG character, and used for synchronisation.
  • If a run of five 1 bits is present in the output stream, a dummy 0 bit is inserted afterwards to prevent normal data from being misidentified as a FLAG. (zero stuffing)

This is the same format used by the Z80 SCC, Motorola MC6854 ADLC, and other similar ICs.

Incoming data stream is clocked into 8-bit sync detection shift register U1 (74LS164). A 1-bit-delayed output from bit zero is tapped and passed to the main data receive shift register U4 (74LS164).

The 8-input NAND gate U2A and inverter U14A form a detector for FLAG characters and stuffed bits. Its output is true (low) when the low six bits of U1's output consist of five 1 bits followed by a 0, i.e. xx11_1110.

The signal from U14A is further decoded by U3B to detect zero-stuffing bits, and by U3C and U14F to detect FLAGs.

To remove zero-stuffing bits, the clock passed to the sync-detector shift register is delayed by U14B and U14C, then AND-ed with the output of the zero-stuffing detector by U3A. This produces the “destuffed clock”, which only contains clock pulses where there are valid data bits. This clock is passed to the main data shift register with the one-bit-delayed data signal as mentioned previously.

The value clocked into U4 is thus the data byte which was originally sent by the headend.

Byte clock recovery

The destuffed bit clock is passed into a divide-by-eight circuit formed of a divide-by-four built from two 74LS74 D-type flip-flops (U22B and U15A) followed by a divide-by-two stage built from another LS74 (U16B).

When a FLAG is received, the FLAG Detect signal resets the counter stage to zero. The inverse FLAG signal is also latched by flip-flop U22A to produce the qualified HDLC flag (HDLC_FLAQ_Q) signal. When this is asserted, U15A and U15B are held in reset for one destuffed bit clock, preventing FLAGs from being erroneously loaded into the FIFO.

U5 PAL16R6 detects broadcast and uniquely addressed packets.

It connects to the rest of the circuit via:

  • Pin 1: Byte clock from U14D. Suppressed for FLAG bytes.
  • Pins 2..9: Incoming data, D7..D0 respectively, from the receive shift register (U4, 74LS164).
  • Pin 12: Receive gate, qualified. Sourced from U32A, set true when the MCU's PB0 output transitions from low to high.
  • Pin 13: P13 status signal, to MCU PC2
  • Pin 14: P14 status signal, to MCU PC3
  • Pins 15 and 16 are internal signals and not connected externally
  • Pin 17..18: State counter. Pin 17 drives FIFO_SO_SET, pin 18 drives FIFO_SO_CLR.
  • Pin 19: HDLC FLAG detect signal. 0 if the current byte was preceded by a FLAG.




The RSSI signal from the demodulator can has a voltage range of around 16V with no signal, to around 1.8V fully saturated (per Jared Boone's video). This enters via pin 3 of the RF block connector. The incoming signal is compared against the threshold level set on trimmer R38. If the signal level is sufficient, the CABLE LED lights.

The voltage divider formed by R43 and R41 reduces the range of the RSSI voltage from 16V to 1.8V to around 0.896 to 0.1V (17.86:1 attenuation, or g=0.056).

The threshold is set by trimmer potentiometer R38, whose top-end voltage is limited by R48, giving an adjustment range from 0V to around 1.163V. A typical preset value is around two-thirds of the range, or around 0.77V. Taking into consideration the attenuation of the resistor divider on the RSSI pin, this means any voltage below around 13.7V will cause the CABLE LED to light.

Opamp U19D compares the attenuated RSSI signal with the set threshold, and lights the CABLE LED if the RSSI signal is below the threshold. Resistor R44 provides positive feedback, adding hysteresis which prevents the CABLE LED from flickering.

This circuit is for user indication only and provides no feedback to the microcontroller or other circuitry.

Pin Function
1 Ground
2 Ground
3 +5V
4 +5V
Pin Function
1 RS422 RX+
2 Ground
3 RS422 TX-
4 RS422 RX-
5 RS422 TX+
Pin Function Connection
1 Ground
2 MC145155 PLL “ENB” (latch enable) input → U31(6805P1).19
3 Received signal strength indication output.
15V for no signal, reduces with increasing signal strength.
→ R43 (RSSI?)
4 MC145155 PLL “CLOCK” output → U10 :?:
5 MC145155 PLL “DATA” output → U10(uA9638).8
6 Ground
7 Demodulator data output → U24.9 (inv) U24.8, U24.11 → (inv) U24.10 → U20(LS164).8
8 Ground
9 Demodulator clock output → U24.5 → (inv) U24.6, U24.3 → (inv) U23.4 → U20(LS164).1
Pin Function
1 MESSAGE LED cathode
2 LINK LED cathode
3 CABLE LED cathode
4 LED anodes
5 POWER LED cathode

This connects to a 6-pin line of pads on the front panel PCB. The pinout is the same, except the Power LED cathode is pin 6, and pin 5 is a no-connect.

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  • Last modified: 2024/04/24 02:29
  • by philpem